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| (R) L4990 L4990A PRIMARY CONTROLLER CURRENT-MODE CONTROL PWM SWITCHING FREQUENCY UP TO 1MHz LOW START-UP CURRENT < 0.45mA HIGH-CURRENT OUTPUT DRIVE SUITABLE FOR POWER MOSFET (1A) FULLY LATCHED PWM LOGIC WITH DOUBLE PULSE SUPPRESSION PROGRAMMABLE DUTY CYCLE 100% AND 50% MAXIMUM DUTY CYCLE LIMIT PROGRAMMABLE SOFT START PRIMARY OVERCURRENT FAULT DETECTION WITH RE-START DELAY PWM UVLO WITH HYSTERESIS IN/OUT SYNCHRONIZATION DISABLE LATCHED INTERNAL 100ns LEADING EDGE BLANKING OF CURRENT SENSE PACKAGE: DIP16 AND SO16W DESCRIPTION This primary controller I.C., developed in BCD60II technology, has been designed to implement off BLOCK DIAGRAM SYNC 1 RCT 2 TIMING 25V DC-LIM 15 MULTIPOWER BCD TECHNOLOGY DIP16 SO16W ORDERING NUMBERS: L4990/L4990A(DIP16) L4990D/L4990AD (SO16W) line or DC-DC power supply applications using a fixed frequency current mode control. Based on a standard current mode PWM controller this device includes some features as programmable soft start, IN/OUT synchronization, disable (to be used for over voltage protection and for power management), precise maximum Duty Cycle Control, 100ns (typ) leading edge blanking on current sense, pulse by pulse current limit and overcurrent protection with soft start intervention. VCC 8 VREF 4 3 DC 14 DIS 2.5V + + T DIS Vref + 16V/10V - PWM UVLO 9 VC 13V BLANKING S R PWM 10 OUT Q OVER CURRENT ISEN 13 + FAULT SOFT-START VREF OK CLK DIS 11 PGND SS 7 1.2V 2.5V + E/A 2R 1V R 12 SGND 6 COMP - 5 VFB D98IN1002 July 1999 1/24 L4990 - L4990A ABSOLUTE MAXIMUM RATINGS Symbol VCC IOUT Parameter Supply Voltage (ICC < 50mA) (*) Output Peak Pulse Current Analog Inputs & Outputs (6,7) Analog Inputs & Outputs (1,2,3,4,5,15,14 13) Power Dissipation @ Tamb = 70C Junction Temperature, Operating Range Storage Temperature, Operating Range Value selflimit 1.5 -0.3 to 8 -0.3 to 6 1 -25 to 125 -55 to 150 Unit V A V V W C C Ptot Tj Tstg (*) maximum package power dissipation limits must be observed PIN CONNECTION SYNC RCT DC VREF VFB COMP SS VCC 1 2 3 4 5 6 7 8 D95IN197 16 15 14 13 12 11 10 9 N.C. DC-LIM DIS ISEN SGND PGND OUT VC THERMAL DATA Symbol Rth j-amb Rth j-amb Parameter Thermal Resistance Junction to Ambient Thermal Resistance Junction to Ambient DIP16 SO16 Value 80 120 Unit C/W C/W PIN FUNCTIONS N. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 2/24 Name SYNC RCT DC VREF VFB COMP SS VCC VC OUT PGND SGND ISEN DIS DC-LIM NC Function Synchronization. A synchronization pulse terminates the PWM cycle and discharges Ct Oscillator pin for external Ct, Rt components Duty Cycle control 5.0V +/-1.5% reference voltage Error Amplifier Inverting input Error Amplifier Output Soft start pin for external capacitor Css Supply for internal "Signal" circuitry Supply for Power section High current totem pole output Power ground Signal ground Current sense Disable. It must never be left floating. Tie to SGND if not used. Connecting this pin to Vref, DC is limited to 50%. If it is left floating or grounded no limitation is imposed Not connected L4990 - L4990A ELECTRICAL CHARACTERISTICS (VCC = 15V; Tj = 0 to 70C; unless otherwise specified.) Symbol VO Parameter Output Voltage Line Regulation Load Regulation TS IOS Temperature Stability Total Variation Short Circuit Current Power Down/UVLO OSCILLATOR SECTION Initial Accuracy Accuracy Initial Accuracy Accuracy Duty Cycle Duty Cycle Tj = 25C; RT = 4.42k; C T = 1nF; pin 15 Vref R T = 4.42K; VCC = 12 to 20V; C T = 1nF; pin 15 = Vref Tj = 25C; RT = 4.42K; C T = 1nF; pin 15 OPEN R T = 4.42K; VCC = 12 to 20V; C T = 1nF; pin 15 OPEN pin 3 = 0,7V, pin 15 = Vref pin 3 = 0.7V, pin 15 = OPEN R T = 4.42k CT = 1nF pin 3 = 3.2V, pin 15 = Vref pin 3 = 3.2V, pin 15 = OPEN pin 3 = 2.02V, pin 15 = OPEN 45 90 37 40 3.0 1.0 VFB to GND VCOMP = VFB VCOMP = 2 to 4V VCC = 12 to 20V Isink = 2mA, VFB = 2.7V Isou rce = 0.5mA, VFB = 2.3V VCOMP > 4V, V FB = 2.3V VCOMP = 1.1V, V FB = 2.7V 5 0.5 2 2 6 1.3 6 4 8 Isen = 0 VCOMP = 5V 0.92 2.85 14 VSS = 0.6V DC = 0% 7 100 3 1.0 100 3 20 200 0.6 3.15 26 15 1.08 2.42 60 0.2 2.5 90 85 1.1 1.0 2.58 43 285 279 280 275 300 300 295 295 315 321 310 315 0 0 kHz kHz kHz kHz % % % % % V V A V dB dB V V mA mA MHz V/s A V ns V/V A A V V ns 3/24 Line, Load, Temperature Vref = 0V VCC = 8.5V; Isink = 0.5mA 4.875 30 0.2 Test Condition Tj = 25C; IO = 1mA VCC = 12 to 20V IO = 1 to 20mA Min. 4.925 Typ. 5.0 2.0 5.0 0.4 5.0 5.125 150 0.5 Max. 5.075 15 20 Unit V mV mV mV/C V mA V REFERENCE SECTION Duty Cycle Accuracy Oscillator Ramp Peak Oscillator Ramp Valley ERROR AMPLIFIER SECTION Input Bias Current VI GOPL SVR VOL VOH IO Input Voltage Open Loop Gain Supply Voltage Rejection Output Low Voltage Output High Voltage Output Source Current Output Sink Current Unit Gain Bandwidth SR Ib IS Slew Rate Input Bias Current Maximum Input Signal Delay to Output Gain SOFT START ISSC ISSD VSSSAT VSSCLAMP SS Charge Current SS Discharge Current SS Saturation Voltage SS Clamp Voltage Internal Masking Time PWM CURRENT SENSE SECTION LEADING EDGE BLANKING L4990 - L4990A ELECTRICAL CHARACTERISTICS (continued.) Symbol OUTPUT SECTION V OL VOH VOUT CLAMP Output Low Voltage Output High Voltage Output Clamp Voltage Collector Leakage Fall Time Rise Time UVLO Saturation SUPPLY SECTION VCCON VCCOFF Vhys IS Iop Iq ISH VZ Startup voltage Minimum Operating Voltage Voltage After Turn-on Hysteresis Start Up Current Operating Current Quiescent Current Shutdown Current Zener Voltage I8 = 20mA Master Operation V1 I1 V1 I1 Vt Clock Amplitude Clock Source Current Sync Pulse Sync Pulse Current Fault Threshold Voltage Shutdown threshold ISOURCE = 0.8mA Vclock = 3.5V Slave Operation Low Level High Level VSYNC = 3.5V OVER CURRENT PROTECTION 1.1 2.4 1.2 2.5 1.3 2.6 V V DISABLE SECTION 3.5 0.8 1 V V mA 4 7 V mA Before Turn-on at: VCC = VCCON - 0.5V CT = 1nF, R T = 4.42k, C O =1nF (After turn on), Co =0nF C T = 1nF, RT = 4.42k, 100 21 IO = 250mA IO = 20mA; VCC = 12V IO = 200mA; VCC = 12V IO = 5mA; VCC = 20V VCC = 20V VC = 24V C O = 1nF C O = 2.5nF C O = 1nF C O = 2.5nF VCC = 0V to VCCON; Isink = 10mA L4990 L4990A L4990 L4990A L4990 L4990A 15 7.8 9 7 5.5 0.5 100 16 8.4 10 7.6 6 0.8 270 12 7.0 270 25 450 18 10 450 30 10 9 10.5 10 13 100 20 35 50 70 200 60 100 1.0 17 9 11 8.2 1.0 V V V V A ns ns ns ns V V V V v V v A mA mA A V Parameter Test Condition Min. Typ. Max. Unit SYNCHRONIZATION SECTION FUNCTIONAL DESCRIPTION The I.C. contains a standard PWM current mode control section with improved performance with respect to the UC384X family. Enhanced features include start-up bias current reduced to < 270A (typ), improved E/A performance (4MHz B/W, 1.3mA Source Current, highslew rate) accurate 1MHz oscillator, and also reduced propagation delays in the critical path from Current Sense to Output. ADDITIONAL FEATURES Soft Start (SS) An external capacitor is charged by an internal constant current source (20A) to generate a SS signal which clamps the E/A output The SS pin doubles as a Fault Reset Delay function as described below. Current Limit / Reset Delay An internal high-speed current limit comparator 4/24 L4990 - L4990A referenced to 1.2V detects primary over-current conditions. On detection of an overcurrent fault the output is immediately shutdown and the fault is also latched. A Fault Reset Delay is implemented by discharging the external Soft Start (SS) timing capacitor before resetting the fault latch and initiating a softstart cycle. In case of a continuous fault condition the SS capacitor is charged to 5V before being discharged again, to ensure that the fault frequency does not exceed the programmed soft start frequency. Duty Cycle Limit A simple connection between the DC-LIM and the available Vref activates an internal T- FlipFlop limiting the DC to about 50%. If this pin is not connected or grounded, the limit of the duty cycle is extended to about 100% Duty Cycle Control Duty Cycle DC is externally programmed by setting a voltage between 1V (0% DC) and 3V (100% DC) at the DC pin. The programmed voltage is compared with the oscillator CT capacitor charging waveform to determine the maximum ON-time in each period. This function gives a fine control of DC. If this pin is floating the maximum duty cycle depends on DC-LIM status. Synchronization A SYNC pin eases Synchronization of the IC to the external world ( e.g. another IC working in parallel or to TV/monitor sync signal). In TV/monitor applications the timing components RT, CT are set for a frequency lower than the minimum TV sync frequency. When the TV circuit has powered-up it takes over and the system frequency is that of the SYNC. Duty Cycle is controllable using the DC function. In parallel operation of several IC's no Master/Slave designation is required as the higher frequency IC is automatically the master. Controllers to be synchronized have their SYNC pins tied together and each SYNC pin operates as a bidirectional circuit. The first IC to drive its SYNC pin is the master and it initiates a discharge of the CT timing capacitor of every controller. The Sync input signal is edge-triggered and sets an internal "sync latch" which ensures full discharge of CT. Disable Function The DIS pin performs a logic level latched-shutdown function. When pulled above 2.5V it shuts down the complete IC with a standby current of <270A (typ). To reset the IC the VCC pin must be pulled-down below the lower UVLO threshold (10V). Leading Edge Blanking (LEB) An LEB interval of 100ns has been incorporated into the IC to blank out the current sense signal during the first 100ns from switch turn-on. This provides noise immunity to turn-on spikes and reduces external RC filtering requirements on the current-sense signal. Figure 1. Quiescent current vs. input voltage. (X = 7.6V and Y = 8.4V for L4990A) Iq [m A ] 30 V1 4 = 0 , O SC= d isa bled Figure 2. Quiescent current vs. input voltage (after disable). Iq [uA] 20 8 6 1 T j = 25 C 300 270 240 0 .8 0 .6 V14 = Vref T j = 25C 210 0 .4 0 .2 0 0 4 8 12 V c c [V] 16 20 24 X Y 8 10 12 14 16 Vcc [V ] 18 20 22 24 5/24 L4990 - L4990A Figure 3. Quiescent current vs. input voltage. Iq [m A ] 9.0 V 14 = 0, V5 = Vref Rt = 4.5Kohm,Tj = 25C Figure 4. Quiescent current vs. input voltage and switching frequency. I q [mA ] 36 30 24 1M Hz 8.5 1M h z 5 0 0K h z 3 0 0K h z 1 0 0 Kh z C o = 1nF, Tj = 25C D C = 0% 8.0 18 500K Hz 7.5 12 300K Hz 100KHz 6 7.0 8 10 12 14 16 18 V cc [V ] 20 22 24 0 8 10 12 14 16 V c c [V ] 18 20 22 Figure 5. Quiescent current vs. input voltage and switching frequency. Iq [mA] 36 Co = 1nF, Tj = 25C Figure 6. Reference voltage vs. load current. Vref [V] 5.1 30 24 18 12 DC = 100% 5.05 1M H z Vcc=15V Tj = 25C 50 0KH z 3 00KH z 5 4.95 10 0KH z 6 0 4.9 0 5 10 Iref [mA] 15 20 25 8 10 12 14 16 Vcc [V] 18 20 22 Figure 7. Vref vs. junction temperature. Vref [V]) 5.1 Figure 8. Vref vs. junction temperature. Vref [V] 5.1 Vcc = 15V 5.05 Vcc = 15V Iref = 1mA 5.05 Iref= 20mA 5 5 4.95 4.95 4.9 -50 -25 0 25 50 Tj (C) 75 100 125 150 4.9 -50 -25 0 25 50 Tj (C) 75 100 125 150 6/24 L4990 - L4990A Figure 9. Vref SVRR vs. switching frequency. SVRR (dB) Figure 10. Output saturation. V sat = V10 [V] 16 120 Vcc=15V Vp-p=1V Vcc = 15V 14 Tj = 25C 80 12 10 40 8 0 1 10 100 1000 fsw (Hz) 10000 6 0 0.2 0.4 0.6 0.8 Isourc e [A] 1 1.2 Figure 11. Output saturation. Vsat = V10 [V ] 2.5 2 1.5 1 0.5 0 Figure 12. UVLO Saturation Ipin10 [mA] 50 Vcc = 15V Tj = 25C 40 30 20 10 0 Vcc < Vccon beforeturn-on 0 0.2 0.4 0.6 Is ink [A] 0.8 1 1.2 0 200 400 600 800 Vpin10 [mV] 1,000 1,200 1,400 Figure13. Timingresistorvs.switchingfrequency. fsw(KHz) 5000 2000 1000 500 200 100 50 20 10 5.6nF 2.2nF Figure 14. Switching frequency vs. temperature. fsw (KHz) 320 Vcc =15V V15 =0V , Tj= 25C 310 Rt= 4.5Kohm, Ct = 1nF Vcc = 15V, V15=Vref 100pF 220pF 470pF 300 290 1nF 280 -50 10 20 Rt (kohm) 30 40 -25 0 25 50 Tj (C) 75 100 125 150 7/24 L4990 - L4990A Figure 15. Switching frequency vs. temperature. fsw (KHz) 320 Rt= 4.5Kohm, Ct = 1nF Figure 16. Dead time vs Ct. Dead time [ns] 1,500 1,200 900 V15 = Vref Rt =4.5Kohm V15 = 0V 310 Vcc = 15V, V15= 0 300 290 600 300 280 -50 -25 0 25 50 Tj (C) 75 100 125 150 2 4 6 8 Timing capacitor Ct [nF] 10 Figure 17. Maximum Duty Cycle vs Vpin3. DC Control Voltage V pin3 [V] 3.5 V15 = Vr ef V15 = 0V Figure18.Delayto outputvs junctiontemperature. Delay to output (ns) 130 120 110 3 2.5 100 2 Rt = 4.5Kohm , 90 Ct = 1nF 1.5 1 0 10 20 30 80 70 PIN10 = OPEN 1V pulse on PIN13 40 50 60 70 Duty C y cle [% ] 80 90 100 60 -50 -25 0 25 50 Tj (C) 75 100 125 150 Figure 19. E/A frequency response. G [dB] 150 120 Phase 140 100 100 80 50 60 0 40 20 0.01 0.1 1 10 100 f (KHz) 1000 10000 100000 8/24 L4990 - L4990A APPLICATION INFORMATION Detailed Pin Functions Description Pin 1. SYNC (In/Out Synchronization). This function allows the IC's oscillator either to synchronize other controllers (master) or to be synchronized to an external frequency (slave). As a master, the pin delivers positive pulses during the ramp-down of the oscillator (see pin 2). In slave operation the circuit is edge triggered. Refer to fig. 21 to see how it works. When several IC Figure 20. Synchronizing the L4990. work in parallel no master-slave designation is needed because the fastest one becomes automatically the master. During the ramp-up of the oscillator the pin is pulled low by a 600A generator. During the ramp-down, that is when the pulse is released, the 600A pull-down is disconnected. The pin becomes a generator whose source capability is typically 7mA (with a voltage still higher than 3.5V). In fig. 20, some practical examples of synchronizing the L4990 are given. RT SYNC 1 L4990 2 RCT CT 4 VREF RT 1 L4990 2 RCT ROSC COSC SYNC L4981A (MASTER) 16 17 18 L4990 (SLAVE) 1 2 RCT CT CT ROSC COSC 4 4 VREF RT RCT 2 L4990 1 (MASTER) SYNC SYNC VREF L4981A (SLAVE) 16 17 18 SYNC (a) (b) D97IN494A (c) Pin 2. RCT (Oscillator). A resistor (RT) and a capacitor (CT), connected as shown in fig. 21 set the operating frequency fosc of the oscillator. CT is charged through RT until its voltage reaches 3V, then is quickly internally discharged. As the voltage has dropped to 1V it starts being charged again Figure 21. Oscillator and synchronization internal schematic. SYNC VREF 4 1 R1 CLAMP RT RCT 2 D1 R3 R2 + 600A D R Q CLK CT 50 D97IN500B 9/24 L4990 - L4990A The frequency can be established with the aid of fig. 13 diagrams or considering the approximate relationship: fosc 1 CT (0.693 RT + KT) (1) R1 DC 3 Figure 22. Duty cycle control. VREF 4 where KT is defined as: 90, V15 = VREF (2) KT = 160 V15 = GND/OPEN and is linked to the duration of the falling edge of the sawtooth: Td 30 10-9 + KT CT (3) T d is also the duration of the sync pulses delivered at pin 1 and defines the upper extreme of the duty cycle range, Dx (see pin 15 for Dx definition and calculation). In case V15 is connected to VREF, however, the switching frequency of the system will be as high as half fosc . If the IC is to be synchronized to an external oscillator, RT and CT should be selected for a fosc lower than the master frequency in any condition (typically, 10-20% ), depending on the tolerance of RT and CT itself. Pin 3. DC (Duty Cycle Control). By biasing this pin with a voltage between 1 and 3 V it is possible to set the maximum duty cycle between 0 and the upper extreme Dx (see pin 15). If Dmax is the desired maximum duty cycle, the voltage V3 to be applied to pin 3 is: V3 = 5 - 2(2-Dmax) (4) Dmax is determined by internal comparison between V3 and the oscillator ramp (see fig. 22), thus in case the device is synchronized to an external frequency fext (and therefore the oscillator amplitude is reduced), (4) changes into: V3 = 5 - 4 exp - RT R2 RCT 2 + TO PWM LOGIC CT D97IN501A Pin 4. VREF (Reference Voltage). An internal generator furnishes an accurate voltage reference (5V1.5%) that can be used to supply an external circuit (consider some ten mA). A small film capacitor (1 F typ.), connected between this pin and SGND, is recommended to preventswitching noise from affecting the reference. Before device turn-on, this pin has a sink current capability of 0.5mA. Pin 5. VFB (Error Amplifier Inverting Input). The feedback signal is applied to this pin and is compared to the E/A internal reference (2.5V). The E/A output generates the control voltage which fixes the duty cycle. The E/A features high gain-bandwidth product, which allows to broaden the bandwidth of the overall control loop, high slew-rate and current capability, which improves its large signal behavior. Usually the compensation network, which stabilizes the overall control loop, is connected between this pin and COMP (pin 6). Pin 6. COMP (Error Amplifier Output). Usually, this pin is used for frequency compensation and the relevant network is connected between this pin and VFB (pin 5). Compensation networks towards ground are not possible since the L4990 E/A is a voltage mode amplifier (low output impedance). See application ideas for some example of compensation techniques. Pin 7. SS (Soft-Start). At device start-up, a capacitor (Css) connected between this pin and SGND (pin 12) is charged by an internal current generator, ISSC, up to about 7V. During this ramp, the E/A output is clamped by the voltage across Css itself and allowed to rise linearly, starting from zero, up to the steady-state value imposed by the control loop. The maximum time interval during which the E/A is clamped, referred to as soft-start time, is approximately: Dmax (5) RT CT fext A voltage below 1V will inhibit the driver output stage. This could be used for a not-latched device disable, for example in case of overvoltage protection (see application ideas). If no limitation on the maximum duty cycle is required (i.e. DMAX = DX), the pin has to be left floating. An internal pull-up holds the voltage above 3V. Should the pin pick up noise (e.g. during ESD tests), it can be connected to VREF through a 4.7k resistor. 10/24 L4990 - L4990A Tss 3 Rsense IQpk Css ISSC As mentioned before, the soft-start intervenes also in case of severe overload or short circuit on the output. Referring to fig. 23, pulse-by-pulse current limitation is somehow effective as long as the ON-time of the power switch can be reduced (from A to B). After the minimum ON-time is reached (from B onwards) the current is out of control. To prevent this risk, a comparator trips an overcurrent handling procedure, named 'hiccup' mode operation, when a voltage above 1.2V (point C) is detected on current sense input (ISEN, pin 13). Basically, the IC is turned off and then soft-started as long as the fault condition is detected. As a result, the operating point is moved abruptly to D, creating a foldback effect. Fig. 24 illustrates the operation. The oscillation frequency appearing on the softstart capacitor in case of permanent fault, referred to as 'hiccup" period, is approximately given by: Thic 4.5 (6) where Rsense is the current sense resistor (see pin 13) and IQpk is the switch peak current (flowing through Rsense), which depends on the output load. Usually, CSS is selected for a TSS in the order of milliseconds. Figure 23. Regulation characteristic and related quantities VOUT D.C.M. C.C.M. A IQpk 1-2 *IQpk IQpk(max) B C TON D T ON(min) D97IN495 1 + 1 Css (7) ISSC ISSD ISHORT IOUT(max) IOUT Since the system tries restarting each hiccup cycle, there is not any latchoff risk. Figure 24. Hiccup mode operation. IOUT SHORT ISEN FAULT SS 5V 0.5V Thic D97IN496 7V time 11/24 L4990 - L4990A Figure25.Turn-on and turn-offspeeds adjustment delivers a voltage internally clamped, as shown in fig. 25. Thus it is possible to supply the driver (pin 9) with higher voltages without any problem of damage for the gate oxide of the external MOS, but, of course, the power dissipation on the IC will increase. In UVLO conditions an internal circuit (shown in fig.26) holds the pin low in order to ensure that the external MOS cannot be turned on accidentally. The peculiarity of this circuit is its ability to mantain the same sink capability (typically, 20mA @ 1V) from VCC = 0V up to the start-up threshold. When the threshold is exceeded and the L4990 starts operating, VREFOK is pulled high (refer to fig. 26) and the circuit is disabled. It is then possible to omit the "bleeder" resistor (connected between the gate and the source of the MOS) ordinarily used to prevent undesired switching-on of the external MOS because of some leakage current. Figure 26. Pull-Down of the output in UVLO. Rg' VCC 8 13V DRIVE & CONTROL 10 OUT Rg VC 9 (V) 17 13 Rg(ON)=Rg+Rg' Rg(OFF)=Rg L4990 D97IN497A 11 PGND "Hiccup" keeps the system in control in case of short circuits but does not eliminate power components overstress during pulse-by-pulse limitation (from A to C). Other external protection circuits are needed if a better control of overloads is required. Pin 8. VCC (Controller Supply). This pin supplies the signal part of the IC. The device is enabled as VCC voltage exceeds the start threshold and works as long as the voltage is above the UVLO threshold. Otherwise the device is shut down and the current consumption is extremely low. An internal Zener limits the voltage on VCC to 25V. Below this value the IC current consumption is low but increases considerably if this limit is exceeded. A small film capacitor between this pin and SGND (pin 12), placed as close as possible to the IC, is recommended to filter high frequency noise. Pin 9. VC (Supply of the Power Stage). It supplies the driver of the external switch and therefore absorbs a pulsed current. Thus it is recommended to place a buffer capacitor (towards PGND, pin 11, as close as possible to the IC) able to sustain these current pulses and in order to avoid them inducing disturbances. This pin can be connected to the buffer capacitor directly or through a resistor, as shown in fig. 25, to control separately the turn-on and turn-off speed of the external switch, typically a PowerMOS. At turn-on the gate resistance is Rg + Rg' and turn-off is Rg only. Pin 10. OUT (Driver Output). This pin is the output of the driver stage of the external power switch. Usually, this will be a PowerMOS, although the driver is powerful enough to drive BJT's (1.6A source, 2A sink, peak). The driver is made up of a totem pole with a highside NPN Darlington and a low-side VDMOS, and 12/24 10 OUT VREFOK 12 SGND D97IN538 Pin 11. PGND (Power Ground). The current loop during the discharge of the gate of the external MOS is closed through this pin. This loop should be as short as possible to reduce EMI and run separately from signal currents return. Pin 12. SGND (Signal Ground). This ground references the control circuitry of the IC, so all the ground connections of the external parts related to control functions must lead to this pin. In laying out the PCB, care must be taken in preventing switched high currents from flowing through the SGND path. Pin 13. ISEN (Current Sense). This pin is to be connected to the "hot" lead of the current sense resistor Rsense (being the other one grounded), to get a voltage ramp which is an image of the current of the switch, (IQ). When this voltage is equal to: L4990 - L4990A V13pk = IQpk Rsense = (VCOMP - 1.4) (8) To increase the noise immunity, a "Leading Edge Blanking" of about 100ns is internally realized as shown in fig. 27. Because of that, the smoothing RC filter between this pin and Rsense could be removed or, at least, considerably reduced. 3 the conduction of the switch is terminated. Figure 27. Internal LEB I 3V 0 CLK ISEN 13 FROM E/A + 1.2V - 2V + - + - PWM COMPARATOR TO PWM LOGIC TO FAULT LOGIC D97IN503 OVERCURRENT COMPARATOR Pin 14. DIS (Device Disable). When the voltage on pin 14 rises above 2.5V the IC is shut down and it is necessary to pull VCC (IC supply voltage, pin 8) below the UVLO threshold to allow the device to restart. When disabled, the current consumption of the IC is as low as before start-up. The pin can be driven by an external logic signal in case of power management, as shown in fig. 28. It is also possible to realize an overvoltage protection, as shown in the section " Application Ideas". If used, bypass this pin to ground with a filter capacitor to avoid spurious activation due to noise spikes. If not, it is advisable to connect the pin to SGND, even though it might be left floating. Pin 15. DC-LIM (Maximum Duty Cycle Limit). The upper extreme, Dx, of the duty cycle range depends on the voltage applied to this pin. Approximately, Dx RT (9) RT + 230 Figure 28. Disable (Latched) DISABLE SIGNAL DIS 14 + - D R Q DISABLE C 2.5V UVLO D97IN502 if DC-LIM is grounded or left floating. Instead, connecting DC-LIM to VREF (half duty cycle option), Dx will be set approximately to: Dx RT (10) 2 RT + 260 and the output switching frequency will be halved with respect to the oscillator one because an internal T flip-flop (see block diagram, fig. 1) is activated. Fig. 29 shows the operation. The half duty cycle option speeds up the discharge of the timing capacitor CT (in order to get duty cycles as close as possible to 50%) so the oscillator frequency - with the same RT and CT will be slightly higher. The halving of frequency can be used to reduce losses at light load in all those systems that must comply with requirements regarding energy consumption (e.g. monitor displays). 13/24 L4990 - L4990A Figure 29. Half duty cycle option. td V15=GND V5=V13=GND V2 DX = tc tc + td tc td V15=VREF V5=V13=GND V10 V2 DX = V10 D97IN498 tc 2 *tc + td tc DEMONSTRATION BOARD To evaluate the device performance, a demonstration board has been realized. Despite its simplicity, it exploits most of the features of the L4990. The board embodies an application based on the following specification of universal mains AC-DC adapter: Input voltage range: 85-270 Vac (50/60 Hz) Output voltage: 15 V Output current: 0.5 to 2A Output voltage ripple : 300 mV (max.) Load regulation: 5% (0.5 to 2 A load change) Target efficiency @ Iout = 2 A: ; 80% over the input voltage full range Some preliminary decisions, concerning topology, operating mode, switching frequency, maximum duty cycle allowed and control technique, have been made. As for topology, at this power level and output voltage, flyback is the most advantageous one, mainly because of its simplicity, which means low parts count, low cost and inherent high efficiency. A peculiar design choice aiming at optimizing the overall system concerns the operating mode: the converter will work in continuous current mode at low input voltages, when input current is greater, and in discontinuous mode at higher input volt14/24 ages. Numerous benefits originate from that. Compared to discontinuous current mode, continuous operation involves lower peak currents (typ. -40%) at the same throughput power. This implies less stress for all power components. The transformer inductance is higher and, therefore, a smaller air gap is required for a given core: this increases primary-to-secondary coupling and, as a consequence, reduces leakage inductance and improves energy transfer. Both efficiency and load regulation will take advantage of that. Another point in favor is a reduction of the minimum output power that the system is able to deliver keeping the output well regulated. Few components are required in addition for slope compensation. Actually, continuous mode flyback suffers also from a poor dynamic behavior during load transients because of the narrow bandwidth of the control loop due to stability problems. However, great dynamic performance is not required to ACDC adapters, so this problem is of no concern. The boundary between the two operating modes has been set at about 150 Vac (@ Iout=2A). The selection of the switching frequency is a matter of trade-off between achieving a small transformer size and high efficiency. 200 kHz seems to be a good compromise. In this application, the wide input voltage range requires a large duty cycle sweep. The higher is the maximum duty cycle, the larger is the operat- L4990 - L4990A ing conditions range, in terms of input voltage and output current, that the converter is able to cover but, on the other hand, the higher is the peak current on the secondary side. As to this point, the L4990 turns out to be particularly useful since it allows to set any maximum duty cycle greater (and lower) than 50% with very good precision. In the present case, a maximum duty cycle of 60% for steady state operation has been selected and an extra 5% is allowed to take transients into account. Since it is not requested a very tight tolerance on the output, the feedback employs a primary side voltage sensing technique to reduce cost and complexity of the circuit. The same technique has been used to protect against output overvoltages. The electric schematic is shown in fig. 30. The PCB layout is shown in figg. 31 and 32. Table 1 and 2 summarize typical system performance, while table 3 lists the relevant bill of material, where details are given only for critical components and/or where useful. Warning: the NTC for inrush current limitation is not assembled, thus use caution when connecting the demo board to the mains directly. The use of a variac or an isolation transformer is recommended. Figure 30. AC-DC adaptor electric schematic Table 1. System efficiency. Iout = 1A Vin (Vac) 85 110 220 270 Vout (V) 14.93 14.95 14.95 14.96 Effic. % 83.7 82.5 81.4 76 Iout = 2A Vou t (V) 14.53 14.55 14.57 14.59 Effic. % 84.3 84.9 85.2 81.6 Table 2. System performance. Line regulation Load regulation Iout = 0.5A to 2A Maximum effic. Output ripple Minimum load Transition Volt. Vin = 85 to 270 Vac Iout = 0.5A Vin = 85 Vac Vin = 270 Vac Vin = 190 Vac Iout = 2A Vin = 85 to 270 Vac Iout = 2A Vin = 270 Vac Vout < 20V From C.C.M to D.C.M Iout = 2A 30mV 0.95V 0.90V 86.2% < 200mV 150mA 160V NTC 85 to 270 Vac B1 T1 C1 R12 R20 C8 R19 C12 D1 R16 15V/2A R13 R1 R2 R15 R21 D3 D4 C2 R17 GND C13 R14 R5 C10 R4 C7 VFB R8 R9 VREF 4 2 R10 C4 RCT SS C5 Q2 R22 7 DC-LIM C6 DCC 3 5 COMP 6 14 DIS 8 VCC 9 R3 R6 C3 D2 VC 10 OUT R7 Q1 R24 L4990 12 15 SGND 13 ISEN R11 11 PGND R23 C15 C14 D97IN499B C11 15/24 L4990 - L4990A Table 3. Components List of the Fig. 30 AC-DC adaptor electric schematic. Component Resistors Reference R1 R2 R3, R14 R4 R5 R6 R7 R8, R9 R10 R11 R12, R13 R15 R16 R17 R19 R20, R21 R22 R23 R24 Capacitors C1 C2 C3 C4 C5 C6, C15 C7, C14 C8 C9 C10 C11 C12 C13 Transformer T1 Value 1.6k 9.1k 10 360k 27k 200k 4.7 4.7k 5.6k 1 24k 330 390 100k 470k 200 2k 1k 100F 330F 47F 1F 1nF 10nF 330pF 330pF 100nF 220nF 100pF 4.7nF 380H ceramic Not used 630V Core: EFD25, Philips, 3F3 ferrite (or equivalent) Primary: 46 T, litz wire 20 x 0.1, interleaved assembly Secondary: 6 T, 4 paralleled litz wire 20 x 0.1 Auxiliary: 7 T (evenly spaced), 0.2 mm GAP ~ 0.7mm ST, TO220 package ST (or equivalent) GI (or equivalent) ST, Shottky, TO220 package ST (or equivalent) ST, F126 package ELU (or equivalent) Not used (see warning) 160V, polypropilene 2%, 1/8W 2%, 1/8W 5%, 1/8W 2%, 1/8W 2%, 1/8W 2%, 1/8W 2%, 1/8W 2%, 1/8W 2%, 1/8W 2%, 1/2W, metallic film (low inductance) 2%, 1/2W 5%, 1/8W Not used 5%,1W, 2 paralleled resistors (not used) 5%, 1W 2%, 1/8W 5%, 1/8W 2%, 1/8W 5%, 1/8W 400V, NCC-SMH or equiv. 25V, NCC-LXF or equiv., 3 paralleled capacitors 25V, electrolytic 10V, electrolytic J precision Description Transistors Diodes Q1 Q2 B1 D1 D2, D3 D4 STP5NA80 2N2222 DF04M STPS20100CT 1N4148 BYT11-600 T2A250V - Fuse NTC Fuse NTC 16/24 L4990 - L4990A Figure 31. AC-DC adaptor PCB layout (1.25 :1 scale) - Component Side. Figure 32. AC-DC adaptor PCB layout (1.25 :1 scale) - Back Side. 17/24 L4990 - L4990A Layout hints. Generally speaking a proper circuitboard layout is vital for correct operation but is not an easy task. Careful component placing, correct traces routing, appropriate traces widths and, in case of high voltages, compliance with isolation distances are the major issues. The L4990 eases this task by putting two pins at disposal for separate current returns of bias (SGND) and switch drive currents (PGND) The matter is complex and only few important points will be here reminded. 1) All current returns (signal ground, power ground, shielding, etc.) should be routed separately and should be connected only at a single ground point. 2) Noise coupling can be reduced by minimizing the area circumscribed by current loops. This applies particularly to loops where high pulsed currents flow. 3) For high current paths, the traces should be doubled on the other side of the PCB whenever possible: this will reduce both the resistance and the inductance of the wiring. 4) Magnetic field radiation (and stray inductance) can be reduced by keeping all traces carrying switched currents as short as possible. 5) In general, traces carrying signal currents should run far from traces carrying pulsed currents or with quickly swinging voltages. From this viewpoint, particular care should be taken of the high impedance points (current sense input, feedback input, ...). It could be a good idea to route signal traces on one PCB side and power traces on the other side. 6) Provide adequate filtering of some crucial points of the circuit, such as voltage references, IC's supply pins, etc. APPLICATION IDEAS Here follows a series of ideas/suggestionsaimed at either improving performance or solving common application problems of L4990-basedsupplies. Figure 33. Isolated MOSFET Drive & Current Transformer Sensing in 2-switch Topologies. VIN VC 9 ISOLATION BOUNDARY 10 OUT L4990 13 ISEN 12 PGND 11 SGND D97IN504 Figure 34. Low consumption start-up VIN 2.2M 33K STD1NB50-1 VCC 22V 47K VREF 4 8 L4990 11 T SELF-SUPPLY WINDING 12 D97IN505A 18/24 L4990 - L4990A Figure 35. Bipolar Transistor Drive VIN VCC 8 VC 9 10 OUT ISEN 13 L4990 11 PGND D97IN506 Figure 36. Typical E/A compensation networks. From VO Ri VFB Rd Cf Rf COMP 6 5 2.5V + 1.3mA + EA 2R R 12 SGND Error Amp compensation circuit for stabilizing any current-mode topology except for boost and flyback converters operating with continuous inductor current. + 1.3mA RP Ri CP Rd Cf VFB Rf COMP 6 5 + EA 2R From VO 2.5V R 12 SGND D97IN507 Error Amp compensation circuit for stabilizing current-mode boost and flyback topologies operating with continuous inductor current. 19/24 L4990 - L4990A Figure 37. Feedback with optocoupler VOUT 6 COMP L4990 5 VFB TL431 D97IN508 Figure 38. Slope compensation techniques V REF RT RCT RSLOPE CT ISEN RSENSE OPTIONAL VREF 4 RT 2 RCT CT 4 10 OUT R R 2 CSLOPE I L4990 13 12 SGND I RSLOPE L4990 ISEN 13 12 SGND OPTIONAL L4990 12 SGND OPTIONAL D97IN509A 13 ISEN RSLOPE RSENSE RSENSE Figure 39. Protection against overvoltage/feedbackdisconnection (latched) RSTART RSTART VCC DIS 8 14 12 SGND VZ DIS 11 PGND D97IN510 VCC 8 14 12 SGND L4990 L4990 11 PGND D98IN904 2.2K 20/24 L4990 - L4990A Figure 40. Protection against overvoltage/feedback disconnection (not latched) RSTART Figure 41. Device shutdown on overcurrent 4 VREF R1 Ipk max 2.5 R SENSE I * 1- R2 R1 Ipk VREF VCC 4 8 DIS 14 L4990 ISEN R2 DC 3 12 L4990 11 11 12 SGND 13 PGND RSENSE OPTIONAL D97IN511A D97IN512A Figure 42. Constant power in pulse-by-pulse current limitation (flyback discontinuous) VIN 80 / 400VDC RFF OUT 10 RFF = 5*10 6 Lp R*Lp RSENSE L4990 11 PGND SGND 12 13 ISEN R RSENSE D97IN513 Figure 43. Voltage mode operation. DC 10K 6 SGND 3 L4990 12 13 ISEN D97IN570A COMP REFERENCES [1] Efficient active Clamp for Off-line Applications using L4990 and L6380 (N.Tricomi, G. Gattavari, C. Adragna, PCIM96 - NURBERG). [2] 25W Off-Line Autoranging Battery Charger with L4990 (AN889) [3] 300W Secondary Controlled Two-Switch Forward Converter with L4990 (AN890) [4] SMPS with L4990 for Multisync Monitors (AN891) [5] High performance VRM using L4990A, for Pentium Pro(R) processor (AN908). 21/24 L4990 - L4990A DIM. MIN. a1 B b b1 D E e e3 F I L Z 0.51 0.77 mm TYP. MAX. MIN. 0.020 1.65 0.5 0.25 20 8.5 2.54 17.78 7.1 5.1 3.3 1.27 0.030 inch TYP. MAX. OUTLINE AND MECHANICAL DATA 0.065 0.020 0.010 0.787 0.335 0.100 0.700 0.280 0.201 0.130 0.050 DIP16 22/24 L4990 - L4990A DIM. MIN. A A1 B C D E e H h L K 10 0.25 0.4 2.35 0.1 0.33 0.23 10.1 7.4 mm TYP. MAX. 2.65 0.3 0.51 0.32 10.5 7.6 1.27 10.65 0.75 1.27 0.394 0.010 0.016 MIN. 0.093 0.004 0.013 0.009 0.398 0.291 inch TYP. MAX. 0.104 0.012 0.020 0.013 0.413 0.299 0.050 0.419 0.030 0.050 OUTLINE AND MECHANICAL DATA 0 (min.)8 (max.) SO16 Wide L h x 45 A B e K H D A1 C 16 9 E 1 8 23/24 L4990 - L4990A Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1999 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 24/24 |
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